In this lab you implement register allocation taking the implementation from the slides as basis.
Implement liveness analysis to determine when (at what instructions) variables are live. Extend the analysis to deal with control flow and loops. This requires a fixed point analysis.
Next implement register allocation bases on the outcome of the liveness analysis. Use the priority queue data structure to represent the interference graph with the nodes representing variables with the most inference listed first. Coloring the graph with a limited number of registers. How do you treat spilling variables to memory?
Extend the fragment of the language that is supported by your compiler with control-flow constructs such as if-then-else and booleans.
Define desugaring rules to reduce the number of constructs that the downstream compiler has to deal with. Consider whether or for which language constructs this is worthwhile; the target machine may have instructions that correspond directly to the source language operators.
Translate the recursive expressions for control flow in ChocoPy to jumps in the control flow graph.
Translate to RISC-V instructions.